1. Field
One embodiment of the present invention relates to a simulator for a logical circuit including a circuit element (timing network) through which a signal transition from a logical value “0” to a logical value “1” (or from a logical value “1” to a logical value “0”) passes after an elapse of a predetermined time period (or the predetermined number of clock cycles).
2. Description of the Related Art
In a logical circuit design, a logic simulator is used to check the propriety of that circuit design before that circuit is actually manufactured as a product using an integrated circuit or the like. As examples of such simulator, the following simulators are known. That is, a logic simulator, which inputs logical connection data, extracts the connection relationship of logical gates as connection information, models a hazard to express a state propagation of each logical gate by a logical value, and simulates generation and propagation of the hazard using a logical gate state propagation table in association with the extracted connection relationship of the logical gates, is known (see FIG. 1 of Japanese Patent Application Publication No. 9-16649: this reference is limited to a hazard function).
Also, a logic simulator, which writes, every time a level transition of an output signal from each element has occurred, at least level transition information which specifies the contents of the level transition and level transition cause information indicating an input terminal to which a test pattern signal that has caused the level transition is input in a storage area corresponding to the element in an information table form, so as to detect a timing error, is known (see FIG. 1 of Japanese Patent Application Publication No. 2-252066).
Furthermore, a logic simulator, which controls a timing error verification means in a timing primitive to recognize input and output signal changes of elements obtained from a signal change of a signal line between elements based on a simulation execution situation, and to execute timing error verification processes with independent contents for respective elements based on the contents of a timing check value definition file, is known (see FIG. 1 of Japanese Patent Application Publication No. 5-128199).
Moreover, a logic simulator, in which a timing check primitive appending means outputs circuit information appended with a timing check primitive only between an input and output of a selected element or a selected loop element based on circuit information with selected element information and circuit information with selected loop circuit information, so as to recognize input and output signal changes of elements obtained from a signal change of a signal line between elements, and to execute detailed timing error verification, is known (see FIG. 1 of Japanese Patent Application Publication No. 5-61931).
In addition, a logic simulator, in which a simulation execution means gives, as a signal value, an error value indicating the presence/absence of a timing error in addition to a logical value to allow influence tracing of an error, is known (see FIG. 1 of Japanese Patent Application Publication No. 4-357569).
As described above, various logic simulators have been conventionally proposed. In the conventional simulator, if there is constraint information “a time period or the number of clock cycles needed for a signal transition to pass through a signal path in a certain logical circuit should be set to be equal to or larger than a specific value or to be equal to or smaller than a specific value”, it is difficult to attain circuit verification including checking as to whether or not elements in a circuit to be simulated violate this constraint information. In other words, it is difficult for the conventional simulator to confirm if the timing constraint of the aforementioned constraint information is proper (the propriety of the timing constraint used in static timing analysis) in accordance with a passing situation of the signal transition (to dynamically confirm when a wrong timing constraint is given).